Siemens EF 88H Series Instrukcja Użytkownika

User’s Manual 04.97C5018-Bit Single-Chip Microcontrollerhttp://www.siemens.de/Semiconductor/

Semiconductor Group 1-4IntroductionC501 Figure 1-4 Pin Configuration P-DIP-40 Package (top view) MCP03215XTAL1XTAL2P2.5/A13SSV281272263254

Semiconductor Group 10-3Device SpecificationsC50110.3 DC Characteristics for C501-1E VCC = 5 V + 10 %, – 15 %; VSS = 0 V; TA = 0 °C to 70 °C for the

Device SpecificationsC501Semiconductor Group 10-4Notes:1)Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

Semiconductor Group 10-5Device SpecificationsC50110.4 AC Characteristics for C501-L / C501-1R / C501-1E VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0

Device SpecificationsC501Semiconductor Group 10-6AC Characteristics for C501-L / C501-1R / C501-1E (cont’d)External Data Memory Characteristics

Semiconductor Group 10-7Device SpecificationsC50110.5 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA =

Device SpecificationsC501Semiconductor Group 10-8AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d)External Data Memory Characteristics

Semiconductor Group 10-9Device SpecificationsC50110.6 AC Characteristics for C501-L40 / C501-1R40 VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 °C to 70

Device SpecificationsC501Semiconductor Group 10-10AC Characteristics for C501-L40 / C501-1R40 (cont’d)External Data Memory Characteristics

Semiconductor Group 10-11Device SpecificationsC501 Program Memory Read CycleMCT00096ALEPSENPort 2LHLLtA8 - A15 A8 - A15A0 - A7 Instr.IN A0 - A7Por

Device SpecificationsC501Semiconductor Group 10-12 Data Memory Read Cycle MCT00097ALEPSENPort 2WHLHtPort 0RDtLLDVtRLRHtLLWLtRLDVtAVLLtLLAX2tRLAZtAVW

IntroductionC501Semiconductor Group 1-5 Figure 1-5 Pin Configuration P-MQFP-44 Package (top view) MCP03216P1.5P1.6P1.7RxD/P3.0N.C.T

Semiconductor Group 10-13Device SpecificationsC501 Data Memory Write Cycle External Clock Drive at XTAL2 MCT00098ALEPSENPort 2WHLHtP

Device SpecificationsC501Semiconductor Group 10-1410.7 ROM Verification Characteristics for C501-1RROM Verification Mode 1

Semiconductor Group 10-15Device SpecificationsC50110.8 OTP Programming and Verification Characteristics for C501-1EVCC = 5 V ± 10%, VSS = 0 V, TA = 2

Device SpecificationsC501Semiconductor Group 10-16 C501-1E OTP Memory Program/Read CycleMCT03237ProgrammingAddressData DataAddresstDVGLtAVGLtGLGHtS

Semiconductor Group 10-17Device SpecificationsC501 AC Testing: Input, Output Waveforms AC Testing: Float WaveformsAC Inputs during testing ar

Device SpecificationsC501Semiconductor Group 10-18 Recommended Oscillator Circuits MCS02452XTAL1XTAL2 XTAL2XTAL1Crystal Oscillator Mode Driving

Semiconductor Group 10-19Device SpecificationsC50110.9 Package Outlines P-DIP-40 Package Outlines Plastic Package, P-DIP-40 for C501G-L

Device SpecificationsC501Semiconductor Group 10-20 P-LCC-44 Package Outlines GPL05882Plastic Package, P-LCC-44 – SMD for C501G-L / C501G

Semiconductor Group 10-21Device SpecificationsC501 P-MQFP-44 Package Outlines Plastic Package, P-MQFP-44 – SMD for C501G-L / C501G-

Semiconductor Group 11-1IndexC50111 IndexNote : Bold page numbers refer to the main definitionpart of SFRs or SFR bits.AAbsolute maximum ratings. . .

Semiconductor Group 1-6IntroductionC5011.2 Pin Definitions and Functions This section describes all external signals of the C501 with its function.

Semiconductor Group 11-2IndexC501MM0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17M1 . . . . . . . . . . . . . . . . . . . . . . . . 3

Semiconductor Group 11-3IndexC501TCON . . . . . . . . . . . . . . . 3-4, 3-5, 6-16, 7-4TF0. . . . . . . . . . . . . . . . . . . . . 3-5, 6-16, 7-4TF1

IntroductionC501Semiconductor Group 1-7P3.0 – P3.7 11,13–19111314151617181910–1710111213141516175, 7–13578910111213I/O Port 3is a quasi-bidirectional

Semiconductor Group 1-8IntroductionC501XTAL2 20 18 14 – XTAL2Output of the inverting oscillator amplifier.XTAL1 21 19 15 – XTAL1Input to the inverting

IntroductionC501Semiconductor Group 1-9PSEN 32 29 26 O The Program Store Enableoutput is a control signal that enables the external program memory to

Semiconductor Group 1-10IntroductionC501 P0.0 – P0.7 43–36 39–32 37–30 I/O Port 0is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

Fundamental StructureC501Semiconductor Group 2-12 Fundamental Structure The C501 is fully compatible to the standard 8051 microcontroller family

Semiconductor Group 2-2Fundamental StructureC5012.1 CPU The C501 is efficient both as a controller and as an arithmetic processor. It has extensive

Fundamental StructureC501Semiconductor Group 2-3Special Function Register PSW (Address D0H) Reset Value : 00H B Register The B register is used

Edition 04.97This edition was realized using the software system FrameMaker.Published by Siemens AG,Bereich Halbleiter, Marketing-Kommunikation, Bal

Semiconductor Group 2-4Fundamental StructureC5012.2 CPU Timing A machine cycle of the C501 consists of 6 states (12 oscillator periods). Each sta

Fundamental StructureC501Semiconductor Group 2-5 Figure 2-7 Fetch Execute Sequence

Semiconductor Group 3-1Memory OrganizationC5013 Memory Organization The C501 CPU manipulates operands in the following four address spaces:– up to 6

Memory OrganizationC501Semiconductor Group 3-23.1 Program Memory, “Code Space” The C501-1R/-1E has 8 Kbytes of read-only/OTP program memory, while t

Semiconductor Group 3-3Memory OrganizationC5013.4 Special Function Registers All registers, except the program counter and the four general purpose

Memory OrganizationC501Semiconductor Group 3-4Table 3-2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents afterRes

Semiconductor Group 3-5Memory OrganizationC501Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Contentafter

Memory OrganizationC501Semiconductor Group 3-6 D0H2)PSW 00HCY AC F0 RS1 RS0 OV F1 PE0H2)ACC 00H.7 .6 .5 .4 .3 .2 .1 .0F0H2)B 00H.7 .6 .5 .4 .3

Semiconductor Group 4-1External Bus InterfaceC5014 External Bus Interface The C501 allows for external memory expansion. To accomplish this, the ex

External Bus InterfaceC501Semiconductor Group 4-2 Figure 4-1 External Program Memory Execution PCLOUTPCHOUTOne Machine Cycle One Machine CycleIN

C501 User’s ManualRevision History : 04.97Previous Releases : 02.96, 08.94, 08.93 (Original Version)Page(previousversion)Page(new version)Subjec

Semiconductor Group 4-3External Bus InterfaceC5014.1.2 TimingThe timing of the external bus interface, in particular the relationship between the cont

External Bus InterfaceC501Semiconductor Group 4-44.2 PSEN, Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activat

Semiconductor Group 4-5External Bus InterfaceC5014.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontrol

System ResetC501Semiconductor Group 5-15 System Reset5.1 Hardware Reset The hardware reset function incorporated in the C501 allows for an e

Semiconductor Group 5-2System ResetC5015.2 Hardware Reset Timing This section describes the timing of the hardware reset signal.The input pin RES

Semiconductor Group 6-1On-Chip Peripheral ComponentsC5016 On-Chip Peripheral ComponentsI/O PortsThe C501 has four 8-bit I/O portst. Port 0 is an open-

Semiconductor Group 6-2On-Chip Peripheral ComponentsC501Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core

Semiconductor Group 6-3On-Chip Peripheral ComponentsC501Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-5). Each I/O line can

Semiconductor Group 6-4On-Chip Peripheral ComponentsC501In fact, the pullups mentioned before and included in figure 6-5 are pullup arrangements as sh

Semiconductor Group 6-5On-Chip Peripheral ComponentsC501The described activating and deactivating of the four different transistors results in four st

Semiconductor Group I-1Table of Contents PageC5011 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Semiconductor Group 6-6On-Chip Peripheral ComponentsC501Port 0, in contrast to ports 1, 2 and 3, is considered as “true” bidirectional, because the po

Semiconductor Group 6-7On-Chip Peripheral ComponentsC5016.1.1.1 Port 0 and Port 2 used as Address/Data Bus As shown in figure 6-7 and below in figu

Semiconductor Group 6-8On-Chip Peripheral ComponentsC5016.1.2 Alternate Functions The pins of ports 1 and 3 are multifunctional. They are port pin

Semiconductor Group 6-9On-Chip Peripheral ComponentsC501Ports 1 and 3 are provided for several alternate functions, as listed in table 6-4: Table

Semiconductor Group 6-10On-Chip Peripheral ComponentsC5016.1.3 Port Handling6.1.3.1 Port Timing When executing an instruction that changes the valu

Semiconductor Group 6-11On-Chip Peripheral ComponentsC5016.1.3.2 Port Loading and Interfacing The output buffers of ports 1, 2 and 3 can drive TTL

Semiconductor Group 6-12On-Chip Peripheral ComponentsC501The reason why read-modify-write instructions are directed to the latch rather than the pin i

Semiconductor Group 6-13On-Chip Peripheral ComponentsC5016.2 Timers/Counters The C501 contains three 16-bit timers/counters, timer 0, 1, and 2, which

Semiconductor Group 6-14On-Chip Peripheral ComponentsC5016.2.1 Timer/Counter 0 and 1 Timer / counter 0 and 1 of the C501 are fully compatible wit

Semiconductor Group 6-15On-Chip Peripheral ComponentsC5016.2.1.1 Timer/Counter 0 and 1 Registers Totally six special function registers control t

Semiconductor Group I-2Table of Contents PageC5016.2.2 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Semiconductor Group 6-16On-Chip Peripheral ComponentsC501Special Function Register TCON (Address 88H) Reset Value : 00H Bit FunctionTR0 Timer 0 ru

Semiconductor Group 6-17On-Chip Peripheral ComponentsC501Special Function Register TMOD (Address 89H) Reset Value : 00H Bit FunctionGATE Gati

Semiconductor Group 6-18On-Chip Peripheral ComponentsC5016.2.1.2 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit time

Semiconductor Group 6-19On-Chip Peripheral ComponentsC5016.2.1.3 Mode 1 Mode 1 is the same as mode 0, except that the timer register is running wi

Semiconductor Group 6-20On-Chip Peripheral ComponentsC5016.2.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automat

Semiconductor Group 6-21On-Chip Peripheral ComponentsC5016.2.1.5 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simpl

Semiconductor Group 6-22On-Chip Peripheral ComponentsC5016.2.2 Timer/Counter 2 Timer 2 is a 16-bit timer / counter which can operate as timer or

Semiconductor Group 6-23On-Chip Peripheral ComponentsC5016.2.2.1 Timer 2 Registers Totally six special function registers control the timer/counter 2

Semiconductor Group 6-24On-Chip Peripheral ComponentsC501Special Function Register T2CON (Address C8H) Reset Value : 00HBit FunctionTF2 Timer 2 Overfl

Semiconductor Group 6-25On-Chip Peripheral ComponentsC501Special Function Register T2MOD (Address C9H) Reset Value : XXXXXXX0B Bit Function–

Semiconductor Group I-3Table of Contents PageC50110 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Semiconductor Group 6-26On-Chip Peripheral ComponentsC5016.2.2.2 Auto-Reload (Up or Down Counter) Timer 2 can be programmed to count up or down when

Semiconductor Group 6-27On-Chip Peripheral ComponentsC501 Figure 6-16 Timer 2 Auto-Reload Mode (DCEN = 1) A logic 1 at T2EX makes timer 2 count

Semiconductor Group 6-28On-Chip Peripheral ComponentsC5016.2.2.3 Capture In the capture mode there are two options selected by bit EXEN2 in SFR T2CO

Semiconductor Group 6-29On-Chip Peripheral ComponentsC5016.3 Serial Interface The serial port is full duplex, meaning it can transmit and receive

Semiconductor Group 6-30On-Chip Peripheral ComponentsC5016.3.1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiproces

Semiconductor Group 6-31On-Chip Peripheral ComponentsC501Special Function Register SCON (Address 98H) Reset Value : 00HSpecial Function Register SBUF

Semiconductor Group 6-32On-Chip Peripheral ComponentsC5016.3.3 Baud Rates Generation There are several possibilities to generate the baud rate clock

Semiconductor Group 6-33On-Chip Peripheral ComponentsC5016.3.3.1 Using Timer 1 to Generate Baud Rates When timer 1 is used as the baud rate genera

Semiconductor Group 6-34On-Chip Peripheral ComponentsC5016.3.3.2 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate genera

Semiconductor Group 6-35On-Chip Peripheral ComponentsC501The timer can be configured for either “timer” or “counter” operation: In the most typical ap

IntroductionC501Semiconductor Group 1-11 IntroductionThe C501-L, C501-1R, and C501-1E described in this document are compatible (also pin-compatible)

Semiconductor Group 6-36On-Chip Peripheral ComponentsC5016.3.4 Details about Mode 0 Serial data enters and exists through RxD. TxD outputs the shi

Semiconductor Group 6-37On-Chip Peripheral ComponentsC501 Figure 6-19 Serial Interface, Mode 0, Functional Diagram MCS02101Internal Bus1SBUFZero De

Semiconductor Group 6-38On-Chip Peripheral ComponentsC501 Figure 6-20 Serial Interface, Mode 0, Timing Diagram S12S3S4S5S6S S6S5S4S3S21S S6S5

Semiconductor Group 6-39On-Chip Peripheral ComponentsC5016.3.5 Details about Mode 1 Ten bits are transmitted (through TxD), or received (through R

Semiconductor Group 6-40On-Chip Peripheral ComponentsC501 Figure 6-21 Serial Interface, Mode 1, Functional DiagramMCS02103Internal Bus1SBUFZero Detect

Semiconductor Group 6-41On-Chip Peripheral ComponentsC501 Figure 6-22 Serial Interface, Mode 1, Timing Diagram MCT02104to SBUFD7Stop BitD6D5D4D3D

Semiconductor Group 6-42On-Chip Peripheral ComponentsC5016.3.6 Details about Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (

Semiconductor Group 6-43On-Chip Peripheral ComponentsC501 Figure 6-23 Serial Interface, Mode 2 and 3, Functional Diagram MCS02105Internal BusTB8SBUF

Semiconductor Group 6-44On-Chip Peripheral ComponentsC501 Figure 6-24 Serial Interface, Mode 2 and 3, Timing Diagram MCT02587Write to SBUFTX Clo

Interrupt SystemC501Semiconductor Group 7-17 Interrupt System The C501 provides 6 interrupt sources with two priority levels. Four interrupts can

Semiconductor Group 1-2IntroductionC501Listed below is a summary of the main features of the C501:• Fully compatible to standard 8051 microcontroller•

Semiconductor Group 7-2Interrupt SystemC5017.1 Interrupt Registers 7.1.1 Interrupt Enable Register Each interrupt vector can be individually

Interrupt SystemC501Semiconductor Group 7-3Special Function Register T2CON (Address C8H) Reset Value : 00H The shaded bits are not used for interru

Semiconductor Group 7-4Interrupt SystemC5017.1.2 Interrupt Request / Control Flags The external interrupts 0 and 1 (INT0 and INT1) can each be e

Interrupt SystemC501Semiconductor Group 7-5The timer 2 interrupt is generated by the logical OR of bit TF2 and EXF2 in register T2CON.Neither of these

Semiconductor Group 7-6Interrupt SystemC5017.1.3 Interrupt Priority Register Each interrupt source can also be individually programmed to one of tw

Interrupt SystemC501Semiconductor Group 7-77.2 Interrupt Priority Level Structure A low-priority interrupt can itself be interrupted by a high-prio

Semiconductor Group 7-8Interrupt SystemC5017.3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled

Interrupt SystemC501Semiconductor Group 7-9Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cyclelabeled

Semiconductor Group 7-10Interrupt SystemC5017.4 External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or

Interrupt SystemC501Semiconductor Group 7-117.5 Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is s

IntroductionC501Semiconductor Group 1-31.1 Pin Configuration This section shows the pin configuration of the C501 in the P-LCC-44, P-DIP-40, and P

Semiconductor Group 8-1Power Saving ModesC5018 Power Saving Modes The C501 provides two basic power saving modes :– Idle mode– Power down mode.8.1

Power Saving ModesC501Semiconductor Group 8-28.2 Idle Mode In the idle mode the oscillator of the C501 continues to run, but the CPU is gated off f

Semiconductor Group 8-3Power Saving ModesC5018.3 Power Down Mode In the power down mode, the on-chip oscillator is stopped. Therefore all functions

Power Saving ModesC501Semiconductor Group 8-48.4 State of Pins in Software Initiated Power Saving Modes In the idle mode and in the power down mode th

Semiconductor Group 9-1OTP Memory OperationC5019 OTP Memory Operation of the C501-1E The C501-1E is the OTP version of the C501-1R ROM version micr

OTP Memory OperationC501Semiconductor Group 9-29.2 Quick-Pulse ProgrammingThe setup for microcontroller quick-pulse programming is shown in figure 9-2

Semiconductor Group 9-3OTP Memory OperationC501Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for anyamount

OTP Memory OperationC501Semiconductor Group 9-49.5 OTP Memory Verification If security bit 2 has not been programmed, the on-chip OTP program memory

Semiconductor Group 10-1Device SpecificationsC50110 Device Specifications 10.1 Absolute Maximum Ratings Ambient temperature under bias (TA) ...

Device SpecificationsC501Semiconductor Group 10-210.2 DC Characteristics for C501-L / C501-1R VCC = 5 V + 10 %, – 15 %; VSS = 0 V; TA = 0 °C to 70 °