Siemens TC65 Dokumentacja Strona 70

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TC65 Hardware Interface Description
Confidential / Released
s
TC65_HD_V02.000 Page 70 of 120 08.06.2006
The timing of a PCM short frame is shown in Figure 29. In PCM mode, 16-bit data are
transferred in both directions at the same time during the first 16 clock cycles after the frame
sync pulse. The duration of a frame sync pulse is one BITCLK period, starting at the rising
edge of BITCLK. TXDAI data is shifted out at the next rising edge of BITCLK. The most
significant bit is transferred first. Data transmitted from RXDAI of the internal application is
sampled at the falling edge of BITCLK.
BITCLK
TXDAI
RXDAI
FS
MSB
MSB
LSB
LSB
14 13
14 13
1
1
12
12
2
2
MSB
MSB
125 µs
Figure 29: PCM timing
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