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TC65 Hardware Interface Description
Confidential / Released
s
TC65_HD_V02.000 Page 8 of 120 08.06.2006
Preceding document: "TC65 Hardware Interface Description" Version 01.030
New document: "TC65 Hardware Interface Description" Version 01.041
Chapter What is new
1.3 Deleted WEEE Directives. Added RoHS logo.
2.1 Completed brief descriptions of pulse counter, ADC, DAC and firmware update.
Deleted specification of power consumption.
2.3 Corrected block diagram.
3.3.1.6 New chapter: Using EMERG_RST Signal to Reset Application(s) or External Device(s)
3.12 Changed Figure 18.
3.16 New chapter: Analog-to-Digital Converter (ADC).
3.17.1 New chapter: Using the GPIO10 Pin as Pulse Counter.
5.1 Updated Table 20: Absolute maximum ratings.
5.5 Completed specifications of EMERG_RST, SYNC, USB. Corrected specifications of
pulse counter, ADC and analog audio interface. Modified Iomax of CHARGEGATE pin.
Preceding document: "TC65 Hardware Interface Description" Version 00.550
New document: "TC65 Hardware Interface Description" Version 01.030
Chapter What is new
1.3 Deleted section “Compliance with international rules and regulations”.
3.3.1.1 Added further details on timing after power-up.
3.3.3.3 New chapter: Turn on/off TC65 Applications with Integrated USB
3.14 Updated Figure 22: Characteristics of SPI modes.
3.15.2,
3.15.2.3
Specified minimum / maximum voltages at MIC pins.
5.1 Corrected ratings for Power Down mode and normal operation.
5.3 Added chapter Storage Conditions.
8.2 Changed note on recommendations for mobile and fixed devices. Added remark on
configuring frequency bands depending on whether or not product is approved for use
in U.S. territories.
Preceding document: "TC65 Hardware Interface Description" Version 00.521
New document: "TC65 Hardware Interface Description" Version 00.550
Chapter What is new
1.3 Added European Directives related to RoHS and WEEE. Updated version numbers of
several standards.
2.1, 3.10,
3.11
Updated bit rates and specification of autobauding.
2.2 Updated figure “TC65 system overview”.
3.14 New chapter: SPI Interface
5.5 Updated specification of ADC1_IN, ADC2_IN, MICP1/MICN1 and MICP2/MICN2
- Hardware Interface Descri 1
- Contents 3
- Figures 6
- 0 Document History 7
- 1 Introduction 10
- 1.2 Terms and Abbreviations 11
- 1.3 Type Approval 14
- 1.4 Safety Precautions 16
- 2 Product Concept 18
- 2.2 TC65 System Overview 21
- 2.3 Circuit Concept 22
- 3 Application Interface 23
- 3.1 Operating Modes 24
- 3.2 Power Supply 26
- 3.3.1 Turn on TC65 28
- 31
- Table 6: Signal states 34
- 3.3.3 Turn off TC65 36
- 3.3.4 Automatic Shutdown 39
- 3.3.4.5 Overvoltage Shutdown 41
- 3.5 Charging Control 43
- 3.5.1 Hardware Requirements 43
- 3.5.2 Software Requirements 43
- 3.5.4 Charger Requirements 45
- 3.6 Power Saving 48
- AT interface disabled 49
- AT interface enabled 49
- 3.8 RTC Backup 51
- 3.9 SIM Interface 52
- 3.10 Serial Interface ASC0 53
- 3.11 Serial Interface ASC1 55
- 3.12 USB Interface 56
- C Interface 59
- Figure 20: I 60
- 3.14 SPI Interface 61
- SPI MODE 0 SPI MODE 1 62
- SPI MODE 2 SPI MODE 3 62
- Clock phase 62
- Clock polarity 62
- 3.15 Audio Interfaces 63
- 3.15.1 Speech Processing 64
- 3.15.2 Microphone Circuit 64
- GSM module 68
- Figure 29: PCM timing 70
- 3.17 GPIO Interface 72
- 3.18 Control Signals 73
- 3.18.4 PWR_IND Signal 75
- 4 Antenna Interface 76
- Antenna 77
- 4.2 Antenna Pad 78
- 4.2.1 Suitable Cable Types 78
- 4.3 Antenna Connector 79
- 5.2 Operating Temperatures 84
- 5.3 Storage Conditions 85
- EMRG_RST 89
- 5.6 Power Supply Ratings 95
- 5.7.4 Voiceband Receive Path 101
- 5.8 Air Interface 103
- 5.9 Electrostatic Discharge 104
- 6 Mechanics 105
- Confidential / Released 106
- 7 Sample Application 111
- 8 Reference Approval 113
- 9 Appendix 115
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