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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 9

2.3 Function Overview (Block Diagram)

Figure 2.3-1 shows the block diagram of the DPC31. The DPC31 has a

bus interface

for connecting an

external micro-processor. It is a parameterizable, synchronous/asynchronous 8-bit interface for various

Siemens, Intel, and Motorola micro-controllers/processors. Via the 13-bit address bus, the user can directly

access the internal 5.5k RAM or the register cells. If the application does not need an external processor,

the ports of the bus interface can be used as I/O. This makes 27 I/O bits available that the internal C31 can

address individually.

The sequence control enters various events (for example, indication events, error events, etc.) in the

interrupt controller

that are signalled to the slave firmware via the interrupt pin. These events can be

enabled individually via a mask register. Acknowledgement is made via the acknowledge register.

The

SSC interface

(SPI)

is used for connecting a serial E

PROM or an A/D converter (such as AD7714).

This interface is laid out only as a master interface.

The

C31 interface

includes the ports of the standard controller. Via this interface, an external memory- and

I/O expansion can be implemented. Via corresponding CS signals, the code and data address areas are

coded out that are not used internally. In addition, up to 13 bits of I/O can be connected via these ports. The

C31/32 emulator (Hitex etc.) is also controlled via this interface.

Via the

, the following are accessed: internal registers, the DPS(DP Slave) control units and the

SSC module. The DPS control units represent the user interface to the DPS layer that is implemented via

individual buffers. These control units exchange the buffers.

The integrated

C31

is fully compatible with the standard microcontroller. Also integrated is a

256 byte data

RAM

. Via a second

interrupt controller

, the interrupt events mentioned above can also be entered in the

C31. This makes it possible to distribute interrupt events between an external and an internal application.

The

bus

physics unit

includes the asynchronous Layer1 (RS485: 9.6kBd to 12 MBd) and the synchronous

Layer1 (IEC 1158-2; Manchester encoded: 31.25kBd) which also allows the chip to be operated in an

intrinsically safe environment.

In the

clock unit

, an analog

PLL

is integrated, to which an external 12MHz quartz must be connected. With

it, the PLL generates the internal 48MHz clock pulse for the asynchronous mode. In the synchronous mode,

the PLL is switched off and an external clock pulse of 4 to 16 MHz is applied. In addition, power

management is implemented in the clock unit which switches off internal clock pulses in certain states. As

outputs, the internal working clock pulse divided by 2 and by 4 is available.

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