Siemens SPC3 Dokumentacja Strona 62

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SchnittStellenCenter
DPC31 HW
Page 60 Version V 1.0
DPC31 HW Description
12/00 Copyright (C) Siemens AG 2000. All rights reserved.
The leading edge of each arriving pulse (2) triggers a timer with the run time t3. The following condition with
regard to time applies:
t1 < t3 < t2
. When t3 expires, the pulse length on t1 and t2 is polled. Depending on
the pulse duration t1 or t2 that was detected respectively, the flipflop FF1 is set to L or H. The output of the
flipflop thus corresponds to the serial data signal RxS1 (4). The output signal (5) of an additional flipflop FF2
is combined with the signal (4) via an or function. When 2 short pulses arrive consecutively, both flipflops are
reset. The or-function results in an L, which is recognized as the end of the static signal RxE1 (6). With the
signal (7), an additional retriggerable timer t4 (40 µs t4 100 µs) resets the two evaluation flipflops during
transmission pauses in order to suppress undefined setting through interference signals.
Pulses of < 0.5 µs that are pending at the comparator output are reliably suppressed; pulses 1 µs are
reliably detected.
Alternative Suggestion regarding Comparator Circuitry:
The wiring of the comparator output described under Figure 7.5-9 has the disadvantage that the comparator
has to be supplied with the external voltage 5V via the input V
IF
, and a level adaptation is necessary at the
output. In addition, a control area up to the positive supply voltage has to be ensured. The circuit variant
below (Figure 7.5-11) avoids these disadvantages. The two voltage dividers R2 / R3 and R4 / R5 move the
work area of the comparator to the center of the internal supply voltage V
CC
; an offset results from the
difference of the values R2 and R4 in the idle state; R6 causes a decrease in amplitude; C2 a delay of the
reference voltage in the active circuit state. The capacitor C1 decouples the external voltage 5V and the
internal V
CC
. This comparator circuit is not integrated into the DPC31 and must be implemented externally.
RxS_IM
anal.
Figure 7.5-11: Wiring of the Comparator with Bridge Network
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