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DPC31 HW

Page 74 Version V 1.0

DPC31 HW Description

No. Parameters Min Max Unit

Address setup time to XRD ↓ or XWR ↓

0ns

XRD ↓ to Data valid (access to RAM)

4T+27 ns

XRD ↓ to Data valid (access to the registers)

4T+27 ns

Address (AB

12..0

) hold time after XRD or XWR ↑

0ns

XCS ↓ Setup time to XRD ↓ or XWR ↓

-5 ns

24 XRD Pulse Width

6T − 10

Data hold time after XRD ↑

38ns

26 Read/Write inactive Time 10 ns

XCS hold time after XRD ↑ or XWR ↑

0ns

XRD/XWR ↓ to XRDY ↓ (normal Ready)

5T + 25 ns

XRD/XWR ↓ to XRDY ↓ (early Ready)

4T + 25 ns

30 XREADY hold time after XRD or XWR 4 25 ns

Data setup time to XWR ↑

10 ns

Data hold time after XWR ↑

10 ns

33 XWR Pulse Width 4T ns

34 XRD, XWR cycle time 6T ns

last XRD ↓ to XCS ↓

4T+10 ns

XCS ↑ to next XWR ↑

4T ns

XWR ↑ to next XWR ↑ (XCS don’t care)

6T ns

Table 9.6-7:

Timing Values in the Asynchronous Intel Mode

XRD

VALID

Data Out

AB(13..1)

DB(7..0)

XCS

XWR = log.'1'

XREADY

(normal)

XREADY

(early)

Figure 9.6-6:

Asynchronous Intel Mode, Processor Read Timing

The Ready signal is generated by the DPC31 synchronously to the clock supplied and reset by the

deactivation the Read or Write signal. With XRD = 1, the data bus is switched to Tristate.

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 93 94

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