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DPC31 HW

Page 70 Version V 1.0

DPC31 HW Description

Signal Name Direction Driver Type Voltage Capacity Load

PA In/Out Tristate 5V tolerant 3 mA 120 pF **

PB In/Out Tristate 5V tolerant 3 mA 80 pF

PC In/Out Tristate 5V tolerant 3 mA 80 pF

PD In/Out Tristate 5V tolerant 3 mA 80 pF

ALE In/Out Tristate 5V tolerant 3 mA 80 pF

XPSEN *** In/Out Tristate 5V tolerant 3 mA 10 pF

XCSDATA Out Tristate 5V tolerant 3 mA 80 pF

XCSCODE Out Tristate 5V tolerant 3 mA 80 pF

PE In/Out Tristate 5V tolerant 9 mA 100 pF

PF In/Out Tristate 5V tolerant 3 mA 100 pF

PG In/Out Tristate 5V tolerant 3 mA 100 pF

PH In/Out Tristate 5V tolerant 3 mA 100 pF

SSCLK Out Tristate 5V tolerant 9 mA 100 pF

SSDO Out Tristate 5V tolerant 9 mA 100 pF

CLKOUT1X2 Out Tristate 5V tolerant 9 mA 50 pF

CLKOUT1X4 Out Tristate 5V tolerant 9 mA 50 pF

RXD_RXS In Tristate 5V tolerant

XCTS_RXA In Tristate 5V tolerant

RTS_TXE Out Tristate 3.3V * 9 mA 50 pF

TXD_TXS Out Tristate 3.3V * 9 mA 50 pF

*) No pull-up resistors! **) including the capacity of the emulation connection (70 pF)

***) XPSEN to be used only for activating the emulator; otherwise, XCSCODE is to be used

Table 9.6-1:

ID Data of the Outputs

If, in reality, the capacitive load deviates from the assumed values, the result will be a change of 0.7

ns maximum per 10pF.

9.6.2 Timing Diagrams, Signal Run Times

In general, the following applies: all signals that start with ‘X’ are ‘low active’.

The signal runtimes are based on the capacitive loads shown in Table 9.6-1.

All timing that refers to the elementary period “T” is defined according to Table 9.6-2.

XPLLEN Comment T

1 Direct Clock Supply 1/CLK

0 Quartz Connection (12 MHz)

⇒ Internal Clock: 48 MHz

20.83 ns

Table 9.6-2:

Definition of the Elementary Period T

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 93 94

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