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DPC31 HW

Page 48 Version V 1.0

DPC31 HW Description

7.3 80C31 Core and Interface

The internal C31 core is SW-compatible with Industrial Standard 8031 (including command execution times).

In addition, it has Timer2 from the 80C32 and the internal work memory consisting of 256 bytes.

Below, this

internal processor is called “C31”

. All functions of the controller can be used by the user except port PD

where the interrupt of the sequential control system is located.

The C31 runs with half of the input frequency (for asynchronous with 24MHz, for synchronous with 2, 4, or 8

MHz).

In order to get the original performance of the C31, Ports A, B, and D must be wired with external pull-

up resistors. Address Port C is always on Output and thus does not have to be wired with pull-up

resistors. The same applies to Port D

(XINT0), Port D

(XWR) and Port D

(XRD).

Notes:

The ports E, F, G and H are configured as input or output channels by the user program if the interface is set

to I/O (BUSTYPE

2..0

= "1 - -").

7.3.1 Reset Phase of the C31

The reset phase of the C31 needs a minimum time span of 30 elementary periods. The build-up time of the

PLL is at 200 µs after the supply voltage and the external quartz have stabilized.

7.3.1.1.1.1.1 Boot Type Setting

In order to start the DPC31, the boot type has to be set.

Presently, only Boot Type 2 is permissible.

BOOT TYPE

Bit 1 Bit 0

0 0 Type 1a

0 1 Type 1b

10Type 2

1 1 Type 3

Table 7.3-1:

Boot Type Settings

7.3.1.2 Boot Type 2

Two variants are possible for Boot Type 2:

1. The internal C31 core processes the program that is stored in the externally connected EPROM (Port A ..

D). Ports E .. H are free and can be used for I/O.

2. The µP/I/O interface (ports E .. H) can be used for connection to an external µP system (with EPROM) or

as I/O channels. Via the SPI interface, an A/D transformer and/or an EPROM can be connected in

addition.

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