Siemens SPC3 Dokumentacja Pobierz pdf (Strona 64)

SchnittStellenCenter

DPC31 HW

Page 62 Version V 1.0

DPC31 HW Description

7.7.3 Response Monitoring

The ‘DP_Control’ mode is used for response monitoring of the DP master (Master_Add). The set monitoring

time is the result of multiplying both watchdog factors and then multiplying by the time base valid at the

moment (1 ms or 10 ms):

= (1 ms or 10 ms) * WD_Fact_1 * WD_Fact_2 (refer to Byte 7 of the parameter assignment message).

The two watchdog factors (WD_Fact_1, WD_Fact_2) and the time base that represent a value for the

monitoring time can be loaded by the user with the ‘Set_Param message’ with any value between 1 and 255.

Exception: the setting WD_Fact_1=WD_Fact_2=1 is not permissible.

This setting is not checked by

the circuit.

With the permissible watchdog factors, monitoring timing between 2 ms and 650s can thus be implemented

regardless of the baudrate.

If the monitoring time expires, the DPC31 reenters ‘Baud_Control’ and the DPC31 generates the

‘WD_DP_Control_Timeout interrupt’. In addition, the state machine is reset; that is, the reset modes of buffer

management are generated.

If another master takes over the DPC31, it either switches to ‘Baud_Control’ (WD_On = 0) or it remains in

‘DP_Control’ (WD_On =1) depending on the enabled response monitoring.

7.8 Clock Supply

7.8.1 PLL

In the asynchronous mode, the clock pulse is generated with an integrated oscillator and an analog-PLL in

the DPC31. The oscillator pins (XTAL1_CLK and XTAL2) are, as shown in Figure 7.8-1, wired with the

values according to Table 7.8.2. The following PLL quadruples the input frequency of 12 MHz (pin XPLLEN =

low). The DPC31 now has the internal system frequency of f

SYS

= 48MHz. It is not possible to connect the

PLL with an external clock pulse generator. The internal system clock has an inaccuracy from the external

quartz (here assumed to be ± 150 ppm) plus the inaccuracy of the PLL (± 400 ppm). The rise time of the PLL

is at 200 µs after the supply voltage and the external quartz have stabilized.

In the synchronous mode, the lower system frequency (f

SYS

= 16/8/4(/2)MHz) is supplied via an external clock

pulse generator directly at pin XTAL1_CLK. The integrated oscillator and the PLL are switched off in that

case (pin XPLLEN = high, power-save mode). (2 MHz system frequency is not enabled.)

To connect an external µProcessor, the output CLKOUT1X2 (f

SYS

/2) and/or CLKOUT1X4 (f

SYS

/4) can be

used. The outputs are active after being switched on -also during the reset phase- and can be switched off

via Mode Register0.

The internal processing clock pulse is f

SYS

/2. The bus physics unit is operated with the scanning frequency

(4-fold for asynchronous, 16-fold for synchronous).

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 93 94

Komentarze do niniejszej Instrukcji

Brak uwag

Siemens SPC3 Dokumentacja Strona 64

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Networking Siemens SPC3