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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 43

WD_State_Changed: The state of the WD_SM has changed (change between

‘Baud_Search, ‘Baud_Control’ or ‘DP_Control’.

Diag_Fetched: The master fetched the diagnostic buffer

IndQ_Entry: An entry was made in the indication queue

IndQ_Full: The Indication_Queue is full. The pending indication could not be

transferred

Go/Leave_Data_Exchange: DPS has entered the ‘Data_Exchange’ mode or has exited it

New_GC_Command: DPS has received a Global_Control message with a modified

‘GC_Command byte’ (New_GC_Int_Mode=0) and has stored this

byte in the RAM cell ‘GC_Command’. If ‘New_GC_Int_Mode=1’,

this interrupt is set for every received Global_Control message.

New_SSA_Data: DPS has received a ‘Set_Slave_Address message’ and has made

the data available in the User_SSA buffer.

New_Prm_Data: DPS has received a ‘Set_Param message’ and has made the data

available in the User_Prm buffer.

New_Cfg_Data: DPS has received a ‘Check_Cfg message’ and has made the data

available in the User_Cfg buffer.

Get_Cfg_Buffer_Changed: Upon request by ‘User_New_Get_Cfg_Buf’, DPS has exchanged

the Get_Config buffers and has made the old buffer available again

to the user.

Diag_Buffer_Changed: Upon request by “User_New_Diag_Buf’, DPS has exchanged the

diagnostic buffers and has made the old buffer available again to

the user.

DX_OUT: DPS has received a ‘Write_Read_Data/GC message’ and made

the new output data available in the N buffer. In the case of

‘Power_On’, ‘Clear’, or ‘Leave_Master’, the DPS_SM makes a

cleared C buffer available and generates this interrupt also. By

parameterizing ‘Enable DX_Out_Port=1’ in the C31_Control

DX_OUT_Overflow: DPS has received a ‘Write_Read_Data/GC message’ and has

made the new output data available in the N buffer. However, the

old data wasn’t fetched and is no longer available. In the sync

mode, the frozen output data in the D buffer was overwritten

because there was no GC message.

RAM_Access_Violation: The memory was accessed outside the communication memory.

SSC_Interface: The SSC interface generated an interrupt.

After reset, the Interrupt is cleared.

Interrupt Register, IR (readable only):

For bit assignment, refer to Interrupt Request Register.

Interrupt Mask Register, IMR (writable, can be changed during operation):

For bit assignment, refer to Interrupt Request Register.

Bit = 1: Mask is set and the interrupt is disabled

Bit = 0: Mask is cleared and the interrupt is enabled.

After reset, all bits are set.

Interrupt Acknowledge Register, IAR ( writable, can be changed during operation):

For bit assignment, refer to Interrupt Request Register.

Bit = 1: The IRR bit is cleared.

Bit = 0: The IRR bit remains unchanged.

After reset, all bits are cleared.

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