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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 35

7 Description of the Hardware Blocks

7.1 Universal Processor Interface

The DPC31 has a parallel 8-bit interface with a 13-bit address bus. It supports all 8-bit processors and micro-

controllers as follows: 80C31/32 by Intel and the Motorola HC11 family. It also supports the 8/16 bit

processors and micro-controllers of the 80C166 family by Siemens, X86 by Intel and the HC16/HC916 family

by Motorola.

In addition, a clock pulse scaler is integrated which makes the internal work clock pulse (divided by 2 (pin

CLKOUT1X2) or 4 (pin CLKOUT1X4) available as system clocks in order to be able to connect a slower

controller without additional effort in a lowcost application (refer to Chapter 7.8.1). Both clock outputs can be

switched off separately via Mode Register1. For asynchronous physics, the DPC31 is wired to a quartz of

12MHz (XTAL1_CLK, XTAL2). An integrated PLL generates the internally needed work clock pulse (48MHz:

refer to Chapter 7.8.1). In the case of synchronous physics, the DPC31 can be operated in a mode that is

particularly low in power loss. This can be achieved only for low clock pulse rates. The PLL is switched off in

this case (XPLLEN = V

) and the variable supply clock pulse of (2), 4, 8, or 16 MHz is applied directly to

XTAL1_CLK.

7.1.1 Bus Interface Unit (BIU)

The BIU is the interface to the connected processor/microcontroller. It allows the CPU accesses to the

internal 5.5kByte dual port RAM and the registers. It is a synchronous or asynchronous 8-Bit interface with a

13-Bit address bus. The interface can be configured via 3 bus type pins (BusType

2..0

) (refer to Table 7.1-1).

With it, the connected processor family (Intel/Motorola bus control signals such as XWR,XRD, and R_W, the

– data format) and the synchronous (rigid) or asynchronous bus timing is specified.

Figure 7.1-1, Figure 7.1-2, Figure 7.1-3, and Figure 7.1-4 show different Intel and Motorola system

configurations. In the C31 mode, the internal address latch and the integrated decoder must be used. In

Figure 7.1-1, the minimum configuration of a system with external µP and DPC31 is shown; the chip is

connected to an EPROM version of the controller. In terms of additional components, only a quartz crystal is

needed in this configuration. If a controller is to be used without integrated program memory, the addresses

have to be latched additonally for the external memory (refer to Figure 7.1-2). The connection diagram in

Figure 7.1-3 applies to all Intel/Siemens processors that offer asynchronnous bus timing and interpret the

Ready signal.

Notes:

If the

DPC31 is connected to an 80286

or something similar, it is to be taken into account that the processer

accesses words; that is, either a swapper is needed that switches, during reading, the corresponding

characters from the DPC31 to the corresponding byte position of the 16-Bit data bus. Otherwise the least

significant address bit is not connected and the 80286 must make word accesses and correspondingly only

interpret the lower byte as shown in Figure 7.1-3.

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 93 94

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