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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 49

ser.

EEPROM

Aktoren

Sensoren

Diagnose

PB-

Inter

face

uP/

I/O-

Inter

face

I/O-

Inter

face

C31-

Erw.

DP/

azyklische

Protokolle

SSC-

Interface

DPC31

Interrupt, Timer

8E/A-Interface

OTP

RAM

UART

ROM

(Flash)

µP-System

(Intel/Motorola)

!! ODER !!

Figure 7.3-1:

Operation in Boot Type 2

7.3.2 80C31 Core and Internal Memory

The processor has an “internal” work memory consisting of 256 bytes.

The data area of the processor is broken down into different blocks (Figure 7.3-2):

The register cells (interrupt controller, DPS control units, etc.) are located from Address 000h to 004Fh.

From Address 0050h to 008Fh, the I/O ports E, F, G, and H can be addressed. From 0090h to 07FFh is an

unused area. The internal RAM follows starting with address 0800h broken down into the block: work cells,

parameter cells, and buffer management, which consists of approx. 0.5 kByte, and the communication area,

which consists of 5.5 kByte.

Starting with 2000h, the external RAM is accessed (signal pin: XCSDATA = low).

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