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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 41

7.1.3 Interface Signals

Pin Name Signal Names Comment

P Interface

IO Interface

Intel

sync.

Intel

async.

Motorol.

sync.

Motorol.

async.

7..0

I/O high-resistance at reset

7..0

15..8

8..1

7..0

IPF

7..0

I/O

4..0

GND AB

13..9

12..8

IPG

4..0

I/O

X/INT X/INT X/INT X/INT O PG

I/O Interrupt, polarity can be

parameterized

XCS XCS XCS I PG

I/O Chipselect

XWR XWR E-Clock GND I PG

I/O Intel: Write / Motorola: E-Clock

XRD XRD R_W R_W I PH

I/O Intel: Read / Motorola:

Read/Write

ALE V

AS I PH

I/O Address Latch Enable

- XRDY - XDSACK O PH

I/O Ready Signal

BUSTYP

2..0

”001” ”000” ”011” ”010” I ”1 - - ” I Setting of the interface

RESET RESET RESET RESET RESET I RESET I Reset input

Table 7.1-3:

Interface Signals for µP and IO Interface

The data bus outputs are high-resistance during the reset phase. In the test mode, all outputs are switched

to high resistance.

7.1.4 Interrupt Controller of the

µP Interface in the DPC31

Via the interrupt controller, the processor is informed of various events. These consist primarily of indication

messages and different error events. The controller has no priorization level and does not provide an

interrupt vector (not compatible with 8259A).

It consists of the following: an interrupt request register (IRR), interrupt mask register (IMR), interrupt register

(IR) and an interrupt acknowledge register (IAR). The structure is shown in Figure 7.1-6.

In the IRR, every event is stored. Via the IMR, individual events can be suppressed. If, for example, the DPS

indications are evaluated only by the internal C31, the corresponding masks have to be set here and enabled

for the C31 in the interrupt controller. The entry in the IRR is independent of the interrupt mask. Events that

are not masked out in the IMR generate the X/INT Interrupt (Pin PG

) via a cumulative network.

For debugging, the user can set every event in the IRR (only those bits are activated that are to be set).

Each interrupt event that was processed by the processor has to be cleared via the IAR (except for

New_Prm_Data, New_DDB_Prm_Data, New_Cfg_Data). A log ‘1’ is to be written to the corresponding bit

position. If a new event and an acknowledgement of the previous event are pending at the same time at the

IRR, the event remains stored. If the processor subsequently enables a mask, it has to be ensured that there

is no past entry in the IRR. To make sure, the position must be cleared in the IRR prior to the mask enable.

Prior to exiting the interrupt routine, the processor has to set the ”End of Interrupt Signal (EOI) = 1” in the

EOI register (see below). With this edge change, the interrupt line is switched inactive. If an event should still

be stored, the interrupt output becomes active again only after an interrupt inactive time of at least 1µs or

1ms, or at most 2µs or 2ms (refer to Chapter 9.6.2.2). Via ‘EOI_Timebase’ (Param Register, refer to Chapter

3.3), this interrupt inactive time can be set (EOI_Timebase=0 -> 1µs; EOI_Timebase=1 -> 1ms). This makes

it possible to reenter the interrupt routine when using an edge-triggered interrupt input.

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