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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 71

9.6.2.1 Clock Supply (XPLLEN = ‘1’)

No. Parameters Min Max Unit

1 Clock High Time 7.5 ns

2 Clock Low Time 9.8 ns

3Rise Time 1 ns

4 Fall Time 1 ns

Table 9.6-3:

Input Clock

CLK

TCLH TCLL

2,4V

0,6V

3 4

Figure 9.6-1:

Clock Timing

9.6.2.2 Clock Outputs

The clock outputs (CLKOUT1X2 and CLKOUT1X4) are active during the RESET also. They are derived from

the PLL (when XPLLEN = ‘0’). The clock outputs thus have the inaccuracy of the PLL (frequency stability:

±400ppm; phase jitter: 1.5ns). Refer also to Chapter 7.8.1.

9.6.2.3 Interrupt

After acknowledging an interrupt with EOI, there is at least a 1us or 1 ms wait in the DPC31 prior to a new

interrupt being read out.

No. Parameters Min Max Unit

1 Interrupt Inactive Time (if EOI_Timebase = 0) 1 2 µs

Interrupt Inactive Time (if EOI_Timebase = 1) 1 2 ms

Table 9.6-4:

Interrupt Inactive Time after EOI

X/INT

EOI

Figure 9.6-2:

Peripheral Mode, Interrupt EOI Timing

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 93 94

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