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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 67

Synchronous: approx. 3 mW at 31.25 kBd and 2MHz clock (C31 switched off)

approx. 3 mW at 31.25 kBd and 2MHz clock (C31 core @ 1MHz)

approx. 5 mW at 31.25 kBd and 4MHz clock (C31 core @ 2MHz)

approx. 20 mW at 31.25 kBd and 8MHz clock (C31 core @ 4MHz)

approx. 43 mW at 31.25 kBd and 16MHz clock (C31 core @ 8MHz)

9.5 Pad Cells

9.5.1 Power-Up of the Supply Voltage

If the DPC31 is used in modules with mixed voltage supply (3.3V and 5V), the voltage difference between the

supply pins (V

= 3.3V ±10%) and the signal pins (V

I/O

) is to be no larger than +3.0V at any time (

I/O

−

< 3.0V). If this value is exceeded, the DPC31 will be destroyed.

max. 3,0V

I/O

Einschalten der

Baugruppe

Ausschalten der

Baugruppe

Figure 9.5-1: Voltage Ramp

9.5.2 Structure of the Pad Cells with 5V Tolerance

The input pad cells used have a tolerance of 5V; that is, they are provided with a protective circuit. This

means that, although they are supplied internally with only 3.3V, the input level may be 5.5V maximum.

Table 9.5-1 shows the operating points.

The 5V-tolerant output pad cells are also provided with a special protective circuit. When driving the 0-level,

there is no difference with respect to the conventional pad cells. The 1-level is driven actively up to V

0.3V.

Starting with this voltage, the external pull-up resistor pulls the level to V

DD2

(5V). This pull-up is needed

only if a 5V-CMOS input is to be driven. For reasons of interference immunity, TTL-level is recommended

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Siemens SPC3 Dokumentacja Strona 69