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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 75

XWR

VALID

AB(13..1)

DB(7..0)

XRD = log.'1'

Data In

XCS

XREADY

(normal)

XREADY

(early)

Figure 9.6-7:

Asynchronous Intel Mode, Processor Write Timing

9.6.2.4.3 Synchronous Motorola Mode (E_Clock mode; for example, 68HC11)

If the DPC31 supplies the CPU with the clock, the output clock has to be 4 times larger than the E_CLOCK.

The DPC31 input clock (CLK) has to be

at least 10 times

larger than the desired system clock (E_Clock).

Therefore, the clock output CLKOUT1x4 that specifies the E_Clock of 3 MHz is to be used (asyn. physics).

The request for a read access to the DPC31 is generated from the rising edge of the E_Clock (in addition:

XCS = ‘0’, R_W = ‘1’) and for a write access from the falling edge of the E_Clock (in addition: XCS = ‘0’, R_W

= ‘0’).

No. Parameters Min Max Unit

40 E_Clock Pulse Width 4T + 67 ns

Address (AB

12..0

) setup time to E_Clock ↑

10 ns

Address (AB

12..0

) hold time after E_Clock ↓

5ns

E_Clock ↑ to Data Active Delay

3ns

E_Clock ↑ to Data valid (access to RAM)

4T + 27 ns

E_Clock ↑ to Data valid (access to the registers)

4T + 27 ns

Data hold time after E_Clock ↓

38ns

R_W setup time to E_Clock ↑

10 ns

R_W hold time after E_Clock ↓

5ns

XCS setup time to E_Clock ↑

0ns

XCS hold time after E_Clock ↓

0ns

Data setup time to E_Clock ↓

10 ns

Data hold time after E_Clock ↓

10 ns

Table 9.6-8:

Timing Values for the Synchronous Motorola Mode

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 93 94

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