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DPC31 HW

Page 18 Version V 1.0

DPC31 HW Description

Param Register:

In the Param Register, individual parameter bits are transferred that are to be changed only in the MAC state

‘Offline’, however. When the request ‘MAC_Start’ (refer to Chapter 5.1.2) is executed, these parameters are

distributed by the sequential control system to the individual modules. Subsequent changes are not taken

into account.

0Early_

Ready

EOI_

Timebase

Quick_Sync

_New

GIM_EN XRTS/

ADD

7 0

0 New_GC_

Int_Mode

Freeze_

Supported

Sync_

Supported

DP_Mode

15 8

En_Change

_Cfg_Puffer

XAsyn/Syn

00 00

1 Preamble

Preamble

27 24

XRTS/ADD: Switchover Output TxE (syn. physics) for different driver control

=0 RTS Signal.

=1 ADD Signal

GIM_EN: Galvanic Isolation Mode for syn. physics

=0 The power-saving interface is switched off

=1 The power-saving interface is switched on (possible only for 31.25kBd)

Quick_Sync_New: Switching on the improved quick sync

=0 The improved quick synchronizer is off.

=1 The improved quick synchronizer is on.

EOI_Timebase: Time base of the EOI timer

=0 The interrupt inactive time is 1 to 2 µsec .

=1 The interrupt inactive time is 1 to 2 msec.

Early_Ready: Early Ready Signal

=0 Ready is generated if the data is valid (Read) or if the data is taken over (write).

=1 Ready is moved ahead by one clock pulse.

DP_Mode: Enable of DPS

=0 DPS is not enabled.

=1 DPS is enabled.

Sync_Supported: Support of Sync_Mode

=0 The Sync_Mode is not supported.

=1 The Sync_Mode is supported. Data is made available in the N-Buffer of the Dout-

SM (not comparable to ASIC LSPM 2).

Freeze_Supported: Support of Freeze_Mode

=0 The Freeze_Mode is not supported.

=1 The Freeze_Mode is supported. Data is frozen from the N-buffer of the Din SM

(not comparable to LSPM 2).

New_GC_Int_Mode: Interrupt Mode for ‘New_GC_Command’

=0 The ‘New_GC_Command Int’ is generated only if there is a change in the

‘GC_Command’ (basic setting).

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