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DPC31 HW

Page 54 Version V 1.0

DPC31 HW Description

PREAMBLE SD FC+DA+SA+Data FCS (CRC) ED

1...8 Byte 1 Byte 1...249 Byte 2 Byte 1 Byte

Figure 7.5-3:

Frame Structure of the Serial Interface

Figure 7.5-4 shows the coding rules . Figure 7.5-5 shows the structure of the preamble and of the delimiters.

These figures show that the elementary characters (= smallest quantization unit) at the transmitter output

have the length of half a bit period. Their generation requires the double bit clock.

Binary "0" Binary "1" NON DATA+ NON DATA-

Figure 7.5-4:

Bit Coding of the

Synchronous Interface

Bit Boundaries

Preamble

(1...8 Byte)

Start Delimiter

End Delimiter

10101010

1N+ N- 1 0N- N+ 0

1N+ N- N- 1 0N+ 1

Figure 7.5-5:

Preamble and Delimiters

The transmitter makes different output signals available (Figure 7.5-5). In addition to the signals RTS (enable

of the send driver) and TxS (send signal), the signal ADD can be utilized. With the combination of TxS and

ADD, an adder circuit for activating a current control unit can easily be established as it is used for the

interface of an intrinsically safe bus station.The combination RxS/TxS is an advantage when activating a

transformer.

It is useful to make the signals RTS and ADD available at a joint output (RTS/ADD). Switching between the

two modes can be parameterized (Param Register; refer to 3.3).

In order to ensure the minimum gap between two messages, the transmitter is disabled at the end of a

message for the duration of a minimum interframe gap time. The gap timer is loaded with the current value

for the interframe gap time from the interframe GAP_Time register (Chapter 3.3).

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