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DPC31 HW

Page 46 Version V 1.0

DPC31 HW Description

PODD: Parity Selection Bit

=0 Even parity bit (parity bit generates in the data byte an even number of

‘1’s).

=1 Uneven parity bit (parity bit generates in the data byte an uneven number of

‘1’s).

BREN: Baudrate Enable Bit

=0 Baudrate generator is disabled (power save).

=1 Baudrate generator is enabled.

Control2 Register:

Bit Position76543210

-----DW

Default 00000000

rrrrrr/wr/wr/w

Bit Function

2..0

Data Width Selection

000: Transfer data with 8 bit length

001: Transfer data with 1 bit length

010: Transfer data with 2 bit length

011: Transfer data with 3 bit length

100: Transfer data with 4 bit length

101: Transfer data with 5 bit length

110: Transfer data with 6 bit length

111: Transfer data with 7 bit length

Status Register:

Bit Position 7 6 5 4 3 2 1 0

BUSY - - - REC-

ERR

PERR RBFU TBEM

Default 00000001

rrrrr/wr/wrr

TBEM: Transmit Buffer Empty Flag

=0 Transmit buffer is full.

=1 Transmit buffer is empty.

RBFU: Receive Buffer Full Flag

=0 Receive buffer is empty.

=1 Receive buffer is full.

PERR: Parity Error Flag

=0 No parity error in data byte.

=1 Parity error in data byte; has to be reset by the user.

RECERR: Receive Error Flag

=0 No receive buffer overflow.

=1 Receive buffer overflow; has to be reset by the user.

BUSY: Busy Flag

=0 No action; SSC module can be reparameterized.

=1 Action on the bus; reparameterization not permitted.

These bits are ORed to the interrupt ‘SSC_Interface’. They must have been enabled in the Interrupt Enable

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 93 94

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