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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 55

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RTS

TxS

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Figure 7.5-6:

Output Signals of the Synchronous Transmitter

7.5.2.2 Receiver

7.5.2.2.1.1.1 Receive Filter

The receive filter conditions the receive signal RxS for clock recovery and for decoding.

7.5.2.2.1.1.2 Manchester Decoder and Clock Recovery

This unit includes all the resources that are needed to decode the data from the filtered receive signal.

The

Clock Recovery

recovers the clock CLK1 from the filtered receive signal and the system clock CLK16

(whose nominal frequency corresponds to the 16-fold data rate).

Because of the ambiguity of the zero crossings

and because of the normally relatively long “catch time” of a

phase control loop, it is necessary to provide the clock recovery with a quick synchronization setup (quick

synchronizer) which, at the beginning of each receive process, quickly synchronizes the recovered clock with

the receive signal.

The signal RxA, generated by the line activity detector, switches the synchronizer into a “quick

synchronization mode” at the beginning of a message. In this mode,

the fourth zero crossing

(or the first

four zero crossings)

of the signal supplied by the preamble filter leads to

resynchronization(Zero_Phase=transition to the initial state) respectively. After the quick synchronization

phase, the receive clock is corrected only with ± 1/16 clock period regarding phase deviation from the signal

FRxS

. This state is retained until the next falling edge of the signal RxA.

The DPC31 has an improved quick synchronizer. To activate it, the user must set the bit

‘Quick_Sync_New=1’ in the param register (refer to Chapter 3.3). In this mode, the DPC31 attempts to more

accurately determine the bit center during the preamble phase by recording the duration of the last high and

low phase before the 4

edge. From the average of these two numbers, it calculates a correction value which

is taken into account when the bit center is specified.

The

data decoder

scans the filtered receive signal with the recovered receive clock (positive edge), and

passes on the scan value, weighted with the polarity information (POL=1, or POL=0) that was transferred by

the decoder state machine as receive signal RxD.

Only the zero crossings in bit center can be utilized for clock recovery.

According to IEC 1158-2 (Chapter 9.6), at least four bits are available to the preamble for synchronization.

Multiple synchronization during this phase does not provide advantages. A decrease in the error frequency

would be attainable through notification via several bits (three maximum)

Through this rigid phase control loop, the required detection according to IEC 1158-2 (Chapter 9.7) of half-

bit slip errors is ensured .

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