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DPC31 HW

Page 78 Version V 1.0

DPC31 HW Description

The Ready signal XDSACK is generated by the DPC31 synchronously to the supplied clock pulse and it is

reset with the deactivation of the AS signal. AS = 1 switches the data bus to Tristate.

VALID

AB(12..0)

DB(7..0)

E_Clock = log.'0'

Data In

R_W

XDSACK

(normal)

XCS

XDSACK

(early)

Figure 9.6-11:

Asynchronous Motorola Mode, Processor Write Timing

9.6.2.5 C31 Memory Interface (internal C31 on external memory)

Symbol Parameters Min Max Unit

LHLL

ALE pulse width

4T − 1.0

AVLL

Address setup to ALE

2T − 8.8

LLAX

Address hold after ALE

2T − 9.7

LLIV

ALE low to valid instr in

8T − 31.6

LLPL

ALE to XPSEN

2T − 4.7

PLPH

XPSEN pulse width

6T − 1.5

PLIV

XPSEN to valid instr in

6T − 27.0

PXIX

Input instruction hold after XPSEN 0 ns

PXIZ

Input instruction float after XPSEN 2T + 4.0 ns

AVIV

Address to valid instr in

10T − 45.6

AZPL

Address float to XPSEN 0 ns

PLSCL

XPSEN to XCSCODE 18.3 ns

SCLSCH

XCSCODE pulse width

6T − 1.5

SCXIX

Input instruction hold after XCSCODE 0 ns

SCXIZ

Input instruction float after XCSCODE

2T − 14.3

for Port A = 120pF; C

for XPSEN = 10pF; C

for all others = 80pF)

Table 9.6-10:

Timing Values for Accesses to Code Memory

1 2 ... 75 76 77 78 79 80 81 82 83 84 85 ... 93 94

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