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DPC31 HW
Page 50 Version V 1.0
DPC31 HW Description
12/00 Copyright (C) Siemens AG 2000. All rights reserved.
External RAM FFFFh
(Data Memory)
2000h
1FFFh
int. CRAM
(5.5 kByte)
S/R_UnitTemp Buffer approx. 09FFh
Internal Stack (for sequential control system)
Buffer Management
Parameter Cells
Internal Variables Start internal RAM
Area that can’t be used
07FFh
0090h
Port H
Direction Register Port H (1 = Input, 0 = Output) 0089h
ByteAddress H
2..0
0088h
BitAddress H
2
0082h
BitAddress H
1
...
BitAddress H
0
0080h
Port G
Direction Register Port G (1 = Input, 0 = Output) 0079h
ByteAddress G
7..0
0078h
BitAddress G
7
0077h
... ...
BitAddress G
0
0070h
Port F
Direction Register Port F (1 = Input, 0 = Output) 0069h
ByteAddress F
7..0
0068h
BitAddress F
7
0067h
... ...
BitAddress F
0
0060h
Port E
Direction Register Port E (1 = Input, 0 = Output) 0059h
ByteAddress E
7..0
0058h
BitAddress E
7
0057h
BitAddress E
6
0056h
BitAddress E
5
0055h
BitAddress E
4
0054h
BitAddress E
3
0053h
BitAddress E
2
0052h
BitAddress E
1
0051h
BitAddress E
0
0050h
DPS Control Units 004Fh
SSC Interface
Parameter Register / Delay Timer
Interrupt Controller 0000h
Figure 7.3-2:
X Data Area of the Internal Processor
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