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DPC31 HW
Page 36 Version V 1.0
DPC31 HW Description
12/00 Copyright (C) Siemens AG 2000. All rights reserved.
BusType
2..0
The DPC31 Processor Interface supports the following micro-controllers:
0 1 1
(synchronous
Motorola)
MOTOROLA micro-controller with the following features:
- Synchronous (rigid) bus; timing without evaluation of XDSACK (PH
2
)
- 8-Bit non-multiplexed bus: DB
7-0
(PE
7..0
), AB
12-0
(PG
4..0
, PF
7..0
)
The following can be connected :
- HC11- types: K, N, M and F1
- HC16- and HC916- types with programmable ECLK timing
- For all other HC11-types with a multiplexed bus, the addresses
AB
7-0
have to be selected externally from the data DB
7-0
.
Address decoder is switched off in the DPC31; CS-signal is supplied from the
outside:
- For micro-controllers with chip select logic: K, F1, HC16, HC916,
the chip selection signals can be programmed regarding the address area,
priority, polarity, and the window width in the write and read cycle.
-For micro-controllers without chip selection logic: N, M and others,
an external chip select logic is needed. This means additional HW effort and
fixed asignments.
Condition:
- The DPC31 output clock (CLKOUT1X2/4) has to be at least four times larger
than the E Clock. The DPC31 clock (48MHz) has to be at least ten times
larger than the desired system clock (E Clock). Pin
CLKOUT1X4 is to be wired with this (E_Clock = 3MHz at 48MHz DPC31
clock).
0 1 0
(asynchronous
Motorola)
MOTOROLA micro-controller with the following features:
- Asynchronous bus; timing with evaluation of XDSACK (PH
2
)
- 8-Bit non-multiplexed bus: DB
7-0
(PE
7..0
); AB
12-0
(PG
4..0
, PF
7..0
)
The following can be connected:
- HC16 and HC916 types
Address decoder in the DPC31 is switched off; CS signal is applied from the
outside
- Chipselect signals are present in all micro-controllers and can be
programmed.
0 0 1
(synchronous
Intel)
INTEL, CPU Basis 80C31/32, micro-controllers of various manufacturers:
- Synchronous (rigid) bus timing without XRDY (PH
2
) evaluation
- 8-Bit multiplexed bus ADB
7-0
(PE
7..0
),
The following can be connected:
- Micro-controller families, such as INTEL, SIEMENS, PHILIPS ...
Address decoder is switched on in the DPC31; CS signal is generated internally:
- The lower address bits AB
7-0
are stored with the ALE signal in an
internal address latch. In the DPC31, the internal CS decoder is
activated that generates its own signal from the addresses AB
12- 0
.
The integrated address decoder is permanently wired, so that the DPC31
Always has to be addressed under the fixed addresses AB
7...0
=000xxxxxb,
Whereby the DPC31 selects the corresponding address window from the
Signals AB
4-0
.
- In this mode, the CS pin (PG
6
) has to be on VDD (high potential)
Wiring: refer to Figure 7.1-1, Figure 7.1-2.
Apply ADB
7-0
to DPC31-Pin PE
7..0
, AB
15-8
to DPC31-Pin PF
7..0,
and the
DPC31-Pin PG
4..0
to VSS.
0 0 0
(asynchronous
Intel)
INTEL and SIEMENS 16/8-Bit micro-controller families
- Asynchronous bus; timing with evaluation of XRDY (PH
2
)
- 8-Bit non-multiplexed bus: DB
7-0
(PE
7..0
); AB
12-0
(PG
4..0
, PF
7..0
)
The following can be connected:
- Micro-controller families; for example, SIEMENS, 80C16x and INTEL X86
Address decoder in DPC31 is switched off; CS signal is applied from the outside
- External address decoding is always required
- External chip selection logic, if not available in micro-controller.
Table 7.1-1
The Different Configurations of the Processor Interface
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