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DPC31 HW

Page 12 Version V 1.0

DPC31 HW Description

3 Memory Assignment

3.1 Memory Area Distribution in the DPC31

Table 3.1-1 shows the distribution of the internal 8k address space of the DPC31. Via this address space,

the user interface to communication (DPS) is mapped. It does not matter whether the user program is

running internally on the C31 or on the external micro-processor; the interface is identical in both cases.

The address area is subdivided into a 2K address space for the register cells and a 6k address space for the

internal RAM. The internal registers (interrupt controller, Mode Register1, DPS control units, SSC interface)

are located in the register area. Certain registers can only be read or written.

The RAM starts at address 800h. In the first area, the internal work cells are located (bit array, variables).

The user is not to access this area. The sequential control system uses these cells for processing the

protocol. Starting with address 0840h, the organizational parameters (parameter cells, buffer ptr(pointer) are

located in the RAM. In the parameter cells, general parameter assignment data is transferred (Param

Score_Register, etc.). The buffer pointers describe the entire buffer management for the SAPs. At address

08A0H, the buffers generated by the user start, corresponding to the parameter assignment of the

organizational parameters. The sequence of the buffers can be selected as required. All buffers or lists must

be located on segment addresses (32 bytes segmentation).

1FFFh

Code Area for the Internal C31

08A0h

Communic-

ation Area

Buffer Area

0840h

Organizational

Parameters

0800h

RAM Internal Work Area

SSC-Interface

Control Unit Parameters

0000h

Table 3.1-1: Memory Area Distribution in the Internal RAM of the DPC31

The stack for the sequential control system needs 64 bytes. A buffer for temporarily storing the receive

message requires 32 bytes.

3.2 Control Unit Parameters (Latches/Registers)

The register cells that are, for example, in the interrupt controller and the DPS control units, are located in the

address area of 0000-003Ch (XDATA). These cells can either be read or written only. The address

assignments are shown in Table 3.2-1. When writing the register cells, the unassigned bit positions are ‘don’t

care’.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 93 94

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