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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 73

In the synchronous Intel mode, the DPC31 stores the least significant address bits with the falling edge of

ALE. At the same time, it expects the most significant address bits at the address bus; from them, it

generates itself a chip select signal.

The request for an access to the DPC31 is generated from the falling edge of the read signal or the rising

edge of the write signal.

XRD

VALID

ALE

AB(15..8)

DB(7..0)

AB(7..0)

Data Out

Addresses

XW R = log.'1'

Addresses

VALID

Figure 9.6-4:

Synchronous Intel Mode, Processor Read Timing

XW R

VALID

ALE

AB(15..8)

Data InAddresses

XRD = log.'1'

Addresses

VALID

DB(7..0)/

AB(7..0)

Figure 9.6-5:

Synchronous Intel Mode, Processor Write Timing

9.6.2.4.2 Asynchronous Intel Mode (X86 Mode)

In 80X86 operation, the DPC31 in principle behaves like a memory with Ready logic; the access timing

depends on the type of access.

The request for an access to the DPC31 is generated from the falling edge of the Read signal or the rising

edge of the Write signal.

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