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DPC31 HW
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DPC31 HW Description
12/00 Copyright (C) Siemens AG 2000. All rights reserved.
M68HC16
DB
DB 15..0
EPRO RAM
AB
AS
R/W
AB 23..0
R/W
AS
IRQ
DSACK
DB 7..0
AB 12..0
Driver, Contro l Logic
Clk
XR eset
DPC31
RESET
Quartz
Scaler :2/4
12 MHz
12/24 MHz
BusType
0 1 0
PE
(7..0)
PG(4..0), PF(7..0)
(12..0)
PH(1)
PH(0)
PG(5)
RTS_TXE
TXD _TXS
RXD_RXS
SER-
Bus
Interface
XCTS_RXA
PH(2)
PG(6)
PG(7)
Gnd
CS
CS
Figure 7.1-5:
M68HC16 System as an Example for Asynchronous Motorola Mode
7.1.2 IO Interface
If the DPC31 is to be operated without external processor, an I/O interface is available instead of the
processor interface (can be set via the bus type pins). This I/O interface consists of four ports (PE
7..0
, PF
7..0
,
PG
7..0
, PH
2..0
). Each port bit can be configured as input or output by the internal application (C31). The
outputs can be addressed bit by bit as well as byte by byte. Reading is always byte by byte. To configure the
I/O bits, each port has a Direction Register (Dir_Reg). The output status is kept in a register bit (refer to
Table 7.1-2). After reset, all ports are switched to input. The addressing of these I/O ports is provided in
Chapter 7.3.2.
BusType
2..0
PH
2..0
PG
7..0
PF
7..0
PE
7..0
1 - -
(I/O Interface)
Dir_Reg_H
2..0
(0=Out;1=In)
Addresses:
Adr_H
2..0
=ByteAddress
Adr_H
0
=BitAddress
Adr_H
1
=BitAddress
Adr_H
2
=BitAddress
Dir_Reg_G
7..0
(0=Out;1=In)
Addresses:
Adr_G
7..0
=ByteAddress
Adr_G
0
=BitAddress
Adr_G
1
=BitAddress
Adr_G
2
=BitAddress
Adr_G
3
=BitAddress
Adr_G
4
=BitAddress
Adr_G
5
=BitAddress
Adr_G
6
=BitAddress
Adr_G
7
=BitAddress
Dir_Reg_F
7..0
(0=Out;1=In)
Addresses:
Adr_F
7..0
=ByteAddress
Adr_F
0
=BitAddress
Adr_F
1
=BitAddress
Adr_F
2
=BitAddress
Adr_F
3
=BitAddress
Adr_F
4
=BitAddress
Adr_F
5
=BitAddress
Adr_F
6
=BitAddress
Adr_F
7
=BitAddress
Dir_Reg_E
7..0
(0=Out;1=In)
Addresses:
Adr_E
7..0
=ByteAddress
Adr_E
0
=BitAddress
Adr_E
1
=BitAddress
Adr_E
2
=BitAddress
Adr_E
3
=BitAddress
Adr_E
4
=BitAddress
Adr_E
5
=BitAddress
Adr_E
6
=BitAddress
Adr_E
7
=BitAddress
Table 7.1-2:
IO Interface on the Processor Interface
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