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DPC31 HW

Page 72 Version V 1.0

DPC31 HW Description

9.6.2.3.1.1.1 Profibus Interface

No. Parameters Min Max Unit

RTS ↑ to TXD Setup Time

XAsyn/Syn = low 4T 4T + T

BIT

XAsyn/Syn = high 0 ns

RTS ↓ to TXD Hold Time

XAsyn/Syn = low 5T 6T ns

XAsyn/Syn = high 0 ns

T:= elementary period

BIT

: elementary period of the transition clock pulse of the Profibus Interface

XCTS_RXA = ‘0’!

Table 9.6-5:

Specification of the Profibus Interface

RTS

TxD

Figure 9.6-3:

Transmit Timing, XCTS constant log. ‘0’

9.6.2.4 µP Interface

9.6.2.4.1 Synchronous Intel Mode (80C32)

No. Parameters Min Max Unit

Address to ALE ↓ Setup time

10 ns

Address (AB

8..15

) hold time after XRD ↑ or XWR ↑

5ns

XRD ↓ to Data Out (access to RAM)

4T+27 ns

XRD ↓ to Data Out (access to the registers)

4T+27 ns

ALE ↓ to XRD ↓

20 ns

Data hold time after XRD ↑

38ns

Data hold time after XWR ↑

10 ns

Data setup time to XWR ↑

10 ns

XRD ↑ to ALE ↑

10 ns

10 XRD Pulse Width

6T − 10

11 XWR Pulse Width 4T ns

Address hold time after ALE ↓

10 ns

13 ALE Pulse Width 10 ns

14 XRD, XWR cycle time 6T + 30 ns

ALE ↓ to XWR ↓

20 ns

XWR ↑ to ALE ↑

10 ns

Table 9.6-6:

Timing Values in the Synchronous Intel Mode

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 93 94

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